`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:33:56 11/15/2024 
// Design Name: 
// Module Name:    Over_Adder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Over_Adder(A,B,C0,C);
	input [3:0]A;
	input [3:0]B;
	input C0;
	output [4:1]C;
	
	wire P0,P1,P2,P3;
	wire G0,G1,G2,G3;
	
	assign G=A&B;
	assign P=A|B;
	
	assign C1=G0|P0&C0;
	assign C2=G1|P1&C1;
	assign C3=G2|P2&C2;
	assign C4=G3|P3&C3;

endmodule
